1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a chip-lead interconnection structure in a semiconductor device.
2. Description of Related Art
Referring to FIG. 1, there is shown a diagrammatic plan view illustrating a lead frame and a semiconductor chip in one example of the prior art semiconductor device (called a "first prior art" hereinafter) having an island die-bonded to a semiconductor chip. This first prior art semiconductor device includes a semiconductor chip 1 die-bonded on an island 11 of a lead frame. Each of bonding pads 2 formed on a periphery of the chip 1 is connected to an upper surface of a corresponding lead 6 of the lead frame by a bonding wire 3.
In the first prior art semiconductor device, since each lead cannot extend beyond a line defined by inner tip ends of the other leads, and since each lead cannot extend into a space between the inner tip end of another lead and the semiconductor chip, the bonding pads 2 are arranged on the periphery of the semiconductor chip 1 in accordance with a pin connection order standardized for each package. In this specification, the lead (of the lead frame), which does not extend beyond a line defined by inner tip ends of the other leads and which does not extend into a space between the inner tip end of another lead and the semiconductor chip, will be called a "normal lead".
FIG. 2A shows a diagrammatic plan view illustrating a lead frame of a lead-on-chip (simply abbreviated an "LOC") type and a semiconductor chip in another example of the prior art semiconductor device, and FIG. 2B shows a diagrammatic sectional view of the prior art semiconductor device shown in FIG. 2A. In these figures, elements corresponding to those shown in FIG. 1 are given the same Reference Numerals.
In this example, a protection film 9 covering an upper surface of a semiconductor chip 1 is adhered and fixed to a lower surface of LOC leads 4 by an electrically insulating adhesive tape 8 provided to extend over and cross a lower surface of a stitch section 5 of the LOC leads 4. Each of bonding pads 2 formed on a periphery of the chip 1 is connected to an upper surface of the stitch section 5 of a corresponding LOC lead 4 by a bonding wire 3. In a zone 7 of inhibiting location of stitch, openings are formed to penetrate through the protection film 9 covering the semiconductor chip 1 so that the bonding pads 2 and others are exposed in the openings.
In the prior art LOC structure, furthermore, selected LOC leads extends over the semiconductor chip 1, as ground (GND) pins L2 shown in FIG. 2A, and on the other hand, a plurality of power supply pads and a plurality of ground pads are located at different desired positions on the semiconductor chip, so that the selected LOC leads are connected at different positions thereof to the plurality of power supply pads and the plurality of ground pads through different bonding wires, respectively, whereby power supply pins and ground pins of the semiconductor device are emphasized.
Moreover, Japanese Patent Application Pre-examination Publication No. JP-A-6-232328, (the content of which is incorporated by reference in its entirety into this application, and also an English abstract of JP-A-6-232328 is available from the Japanese Patent Office and the content of the English abstract of JP-A-6-232328 is also incorporated by reference in its entirety into this application), discloses another LOC structure semiconductor device (called a "second prior art" hereinafter). As shown in FIG. 1 of JP-A-6-232328, the second prior art includes power supply pads 5a and 5b and signal pads 6 which are arranged on a surface of a semiconductor chip 1 to form a plurality of rows. A lead 2 (of a lead frame) for a first power supply and a lead 3 (of the lead frame) for a second power supply are arranged to extend between the rows of the power supply pads 5a and 5b and the signal pads 6. Leads 4 (of the lead frame) for signal lines are located at respective outsides of the rows of the power supply pads 5a and 5b and the signal pads 6.
In the LOC structure semiconductor device disclosed in JP-A-6-232328, since the power supply pads 5a and 5b and the signal pads 6 are arranged in the plurality of rows on the surface of the semiconductor chip 1 and since the lead 2 (of the lead frame) for the first power supply and the lead 3 (of the lead frame) for the second power supply are arranged to extend between the rows of the power supply pads 5a and 5b and the signal pads 6, the power supply pads 5a and 5b can be connected to the leads 2 and 3 for the first and second power supplies at desired discretionary positions of the leads 2 and 3 for the first and second power supplies, so that a power supply line length in the semiconductor chip 1 from the power supply pads 5a and 5b to circuit elements internally incorporated in the semiconductor chip 1, can be shortened, with the result that an internal power supply line resistance in the semiconductor chip 1 can be reduced. In addition, since a signal line length in the semiconductor chip 1 from the signal pad 6 to a circuit element internally incorporated in the semiconductor chip 1 can be shortened, an input capacitance of a signal input can be reduced, and therefore, a drop of an operation speed of the semiconductor device can be prevented.
In the first prior art semiconductor device mentioned above, since the lead frame is so configured that each lead cannot extend beyond a line defined by tip ends of the other leads and each lead cannot extend into a space between a tip end of another lead and a semiconductor chip, bonding pads must be arranged on the semiconductor chip in accordance with a pin connection order standardized for each package.
In this first prior art, if it was possible to locate a plurality of power supply pads and a plurality of ground pads at different arbitrary positions, it is possible to shorten the wiring length within the semiconductor chip from each of the power supply pad and the ground pad from a corresponding circuit element within the semiconductor chip, thereby to reduce the wiring resistance of the power supply line and the ground line. However, the lead frame of the first prior art does not allow to locate a plurality of power supply pads and a plurality of ground pads because of the reason as mentioned above. Therefore, in order to emphasize the power supply pad and the ground pad, there is only the way of increasing the width of wiring conductor so as to prevent an increase of the wiring resistance of the power supply line and the ground line within the semiconductor chip. But, this way inevitably results in an increased area of the semiconductor chip.
As a countermeasure for overcoming the above mentioned disadvantage, the LOC structure can be adopted as in the second prior art as mentioned above. In this LOC structure, the power supply lead and the ground lead of the lead frame can be caused to extend over the semiconductor chip, so that the power supply lead and the ground lead can be connected at desired positions thereof through bonding wires to a plurality of power supply pads and a plurality of ground pads located at arbitrary positions on the semiconductor chip. As a result, the power supply line length in the semiconductor chip from the power supply and ground pads to circuit elements internally incorporated in the semiconductor chip can be shortened, so that an internal wiring resistance in the semiconductor chip can be reduced, with the result that the power supply pin and the ground pin can be emphasized.
In the second prior art, however, it is necessary to locate the stitch section of leads of all pins on the semiconductor chip. On the other hand, there is a tendency that the number of pins will increase in future because of further microminiaturization of the semiconductor device, increase of the pin number itself and advancement of the multi-function. This tendency causes the following serious disadvantages in the prior art LOC structure.
A first disadvantage is that: With the increased number of pins, the number of stitch sections relatively increases as compared with the semiconductor chip size. Under this circumstance, even when it was attempted to extend the leads of the power supply pin and the ground pin over the semiconductor chip so that the leads of the power supply pin and the ground pin are connected at desired positions thereof through bonding wires to power supply pads and ground pads located at arbitrary positions of the semiconductor chip in order to emphasize the power supply pin and the ground pins, all of the stitch sections cannot be carried on the semiconductor chip, with the result that some of the stitch sections must be crowded out of the surface of the semiconductor chip. In this condition, it is no longer possible to assemble in the LOC structure, and therefore, it is becomes resultantly impossible to emphasize the power supply pin and the ground pin.
A second disadvantage is that: In the prior art LOC structure, it is necessary to locate, on the semiconductor chip, all leads including not only the power supply lead and the ground lead but also the signal leads. On the other hand, for a high speed access, the signal leads are essentially desired to be at a low resistance and at a low capacitance. However, if the signal lead is extended to have an elongated lead length, an extra inductance, and an extra capacitance and an extra resistance are added to the signal lead, with the result that a delay time between the signal pin and the signal pad increases.
A third disadvantage is that: In the prior art LOC structure, all the LOC leads extend beyond the periphery of the semiconductor chip onto the semiconductor chip by passing between the bonding pads. Therefore, the increase of the LOC leads means the increase of the LOC leads passing between the bonding pads, and accordingly, the pitch of the bonding pads is limited by the number of the LOC leads passing between the bonding pads. Although it is possible to technically reduce the pitch of the bonding pads in a design of the semiconductor device, the location of the bonding pads is restricted by the number of the LOC leads passing between the bonding pads, with the result that the degree of freedom in a layout design is restricted, and the semiconductor chip size is inevitably increased.